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发明授权
CN100578441C 实现并行数据排序的硬件电路及方法 失效 - 权利终止

实现并行数据排序的硬件电路及方法
摘要：
本发明公开了一种实现并行数据排序的硬件电路及方法。将n个寄存器中每相邻两个单元编为一组，从编号为0的单元开始；对同一组内的两个单元中的数据进行比较，并将数值比较小的数据存储于编号较小的单元内，而值比较大的数据存储于编号较大的单元内；将编号为0的单元单独编为一组，从编号为1的单元开始将寄存器A中每相邻两个单元编为一组；对同一组内的两个单元中的数据进行比较，并将数值比较小的数据存储于编号较小的单元内，数值比较大的数据存储于编号较大的单元内；重复以上操作n次。采用本发明的上述电路及方法，极大的缩短了硬件排序所需周期数，可以实现在n个时钟周期内完成对n个数据的排序。
摘要（英）：

The invention discloses a hardware circuit for realizing the seriation of parallel data and a method. Each adjacent two units in n registers are arranged as one group, which is started from the unit with the serial number of 0; the data of the two units in the same group are carried out the comparison, the data with the smaller value is stored in the unit with the smaller serial number, the data with the bigger value is stored in the unit with the bigger serial number; the unit with the serial number of 0 is independently arranged as a group, each adjacent two units in the register A are arranged as one group from the unit with the serial number of 1; the data of the two units in the same group are carried out the comparison, the data with the smaller value is stored in the unit with the smaller serial number, the data with the bigger value is stored in the unit with the bigger serial number; and the operations above are repeated for n times. The usage of the circuit and the method of the invention can greatly shorten the number of the cycles for the seriation of the hardware and complete the seriation of n data in n clock cycles.

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