The invention relates to a validating method and a system that a gate array can be programmed and a logic block can be configured on the spot, and the invention relates to the technology of an integrate circuit. The invention comprises the steps as follows: firstly, a CLB test vector, namely, a predefined result mapping table is predefined and stored in a software part; secondly, configuration files are automatically generated one after another in the software part according to the CLB test vector, the predefined result mapping table. The configuration files are transmitted to a hardware partand are configured. The CLB which is not tested at present are closed by the hardware part according to the configuration files, only the testing target CLB is preserved; thirdly, the CLB test vectoris imposed for the hardware part FPGA by the software part according to the CLB test vector, the predefined result mapping table, and the hardware part FPGA makes a reply to the test vector. The results are returned to the software part by the hardware part, and the results are analyzed and compared by the software part to create a testing report. The beneficial effects of the invention are that the condition that a plurality of CLBs making mistakes at the same time can be exactly positioned and validated. Simultaneously, the invention can automatically complete the test for all of the CLB. The test efficiency is greatly improved, and online programmable effect with high efficiency is realized.