Being related to master/slave devices, the method includes steps: (1) master device sends clock signal, synch signal, and data to slave device; (2) when receiving data, the slave device transmits thesynch signal received at same time to the master device; after receiving the transmitted synch signal from the slave device, the master device returns the synch signal back to the slave device; (3) using the received clock signal, the slave device counts value of transmission delay (VTD) between the received synch signal and the returned synch signal; (4) using the received synch signal as reference and based on VTD, the slave device adjusts preact of time for sending data to the master device; (5) based on clock signal and synch signal, the master device extracts the received data. The invention prevents signal error from transmission delay of synch signal caused by long transmission line as well as overcomes too high demand on hardware and processing capabilities.