It is a distributed processing system clock synchronization method, in which the programmable logic device of the control unit sends the counting clock and interrupt signal to the programmable logic device of the business processing unit, and according to the interrupt signal, the business processing unit resets the counter to its initial value, and in accordance with the said counting clock, achieves the cycle counting of the counter, thus achieving clock synchronization of the control unit and the business unit. The invention solves the precise clock synchronization problem, and the advantage is due to the clock to generate accurate time is the same clock source and therefore no time deviation, and no need frequently synchronization action, and meanwhile, as the synchronization using hardware signal line interruption, it can ignore the synchronized delay.