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发明公开
CN101099121A 高效率DC-DC同步降压转换器 无效 - 撤回

高效率DC-DC同步降压转换器
摘要：
本发明揭示一种效率得到提高的DC-DC功率调节器电路，例如同步降压DC-DC转换器电路(80)。提供功率级，其具有用于接收DC输入电压的输入端口并具有用于提供经调节的DC输出电压的输出端口。所述功率级包括控制FET晶体管(Q1)，所述控制FET晶体管(Q1)具有第一端子、第二端子和栅极，第一端子连接至所述输入端口。储能元件(Lo)具有连接至控制FET输出端子的第一端子和连接至所述输出端口的第二端子。被驱动的FET晶体管(Q2)具有连接至地的第一端子、连接至所述储能元件的第一端子的第二端子、以及栅极。驱动器电路(81)具有适于接收控制信号的输入端，并向控制FET栅极提供第一驱动器信号以及向被驱动的FET栅极提供第二驱动器输出信号。驱动器电路具有用于接收电能以给驱动器电路供电的电源节点，所述电源节点连接至转换器电路外部的电源。驱动器供电电路经布置以从储能元件的第一端子获得电能，并在转换器电路的初始运行周期之后将电能提供至驱动器电路的电源节点。
摘要（英）：

A DC-to-DC power regulator circuit, such as a synchronous buck DC-to-DC converter circuit (80), having improved efficiency. A power stage is provided, having an input port for receiving a DC input voltage and having an output port for providing a regulated DC output voltage. The power stage includes a control FET transistor (Q1) having a first terminal, a second terminal, and a gate, the first terminal being connected to the input port. An energy storage element (Lo) has a first terminal connected to the control FET output terminal and a second terminal connected to the output port. A driven FET transistor (Q2) has a first terminal connected to ground, a second terminal connected to the first terminal of the energy storage element, and a gate. A driver circuit (81) has an input adapted to receive a control signal, and provides first driver signal to the control FET gate and a second driver output signal to the driven FET gate. The driver circuit has a power supply node for receiving power to power the driver circuit, which is connected to a power supply external to the converter circuit. A driver powering circuit is arranged to derive power from the first terminal of the energy storage element and provide it to the power supply node of the driver circuit after an initial period of operation of the converter circuit.

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