The present invention discloses a reduced instruction set computer (RISC) processor device and the data processing method thereof. The device comprises a decoder, a physical register file and an operational unit, as well as a data path connected among the decoder, the physical register file and the operational unit, wherein, each physical register in the physical register file is extended to 72 bits, and the whole data path is uniformly expanded to 72 bits; the operational unit comprises an extended operational module which is used in instruction operation to modify the flag bit of the 72-bitregister in the physical register file and to carry out new instruction operation according to the modified flag bit. The present invention expands the optimization space of virtual machines and achieves the objective of improving the performance of virtual machines.