The invention discloses a processor for parallel processing of a plurality of threads and a method for the processor to process a plurality of threads parallelly. The threads can come from different applications in the processor for parallel processing of a plurality of threads. The processor comprises a structural memory, which provides independent instructions and data storage for a plurality of threads; an instruction issuance unit, which reads the instructions of a plurality of threads and issues the instructions to an execution engine; the execution engine, which, shared by a plurality of threads, executes the instructions from the instruction issuance unit. The processor and the method of the invention avoid the necessity of execution pipeline reproduction in dual core proposals, allow better utilization of hardware resources and achieve better load equilibrium among a plurality of processed threads, thereby greatly lowering the chip cost.