The invention discloses a method for fabricating a nano-scale CMOS integrated circuit based on micron-scale processing technique. The method includes the following steps: fabricating an N/P well and growing a Poly-Si/ SiN/Poly-Si multi-layer structure on the N/P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiO2; etching the SiO2layer on the surface, except the SiO2 at the side of the window; based on the etching ratio of Poly-Si to SiN(11:1), etching the Poly-Si on the upper layer; based on the etching ratio of SiN to SiO2 (2:1), etching the SiN outside the protective area on the side wall of SiO2; based on the etching ratio of Poly-Si to SiO2(50:1), etching the Poly-Si outside the protective area on the side wall of SiO2 so as to form an n/p MOSFET grid; injecting ions, self-aligning, and forming the source area and the drain area of the n/p MOSFET grid so as to form an n/p MOSFET device; and photoetching interconnection lines of the device so asto form a CMOS integrated circuit with a conducting channel at 45-90nanometer. The invention can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.