The invention provides a high speed associate processor interface of an embedded processor, comprising a first grade pipeline, a second grade pipeline and a third grade pipeline which are connected in sequence; wherein the first grade pipeline comprises a processor preserving stack and a command buffer, two associate processor commands are cached at most when the associate processor interface andthe data of an external associate processor are in an interchange state, and current executable associate processor command is selected from the preserving stack and the command buffer to be transmitted to the next grade pipeline; the second grade pipeline comprises the functions of controlling logic, generating relevant associate processor to select and read/write signals, communicating data andtransmitting the result to the next grade pipeline when the data read/write operation of the associate processor is finished; the third grade pipeline comprises the functions of sending data write back request to the embedded processor and feeding the result back to the embedded processor by an universal data bus. The invention increases the data transmission speed between the CPU and the associate processor and improves the performance of the processor.