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发明授权
CN101625891B 一种高密度、高鲁棒性的亚阈值存储单元电路 有权 转让

一种高密度、高鲁棒性的亚阈值存储单元电路
摘要：
一种高密度、高鲁棒性的亚阈值存储单元电路，设有两个PMOS管P1、P2及五个NMOS管N1～N5，两个PMOS管及NMOS管N3、N4、N5的各体端均与本晶体管的栅端连接；NMOS管N1、N2的体端接地；NMOS管N1与PMOS管P1和NMOS管N2与PMOS管P2分别组成两个反相器，两个反相器之间通过关断NMOS管N5将两个反相器连接成交叉耦合，N1、P1反相器的输出端直接连接到N2、P2反相器的输入端，N2、P2反相器的输出端经由关断NMOS管N5连接到N1与P1反相器的输入端；NMOS管N3连接N1、P1反相器的与写位线，NMOS管N4连接N2、P2反相器的与写位线的非和读字线。
摘要（英）：

The invention relates to a sub-threshold storing unit circuit with high density and high robustness, which is provided with two PMOS pipes P1 and P2 and five NMOS pipes N1-N5. Body ends of the two PMOS pipes and the NMOS pipe N3, N4 and N are connected with grid ends of a transistor. Body ends of the NMOS pipes N1 and N2 are grounded; and the NMOS pipe N1 and the PMOS pipe P1 as well as the NMOS pipe N2 and the PMOS pipe P2 respectively form two phase inverters. The two phase inverters are connected into cross coupling by the cut-off NMOS pipe N5. An output end of the N1-P1 phase inverter is directly connected with an input end of the N2-P2phase inverter. An output end of the N2-P2phase inverter is connected with an input end of the N1-P1 phase inverter by the cut-off NMOS pipe N5. The NMOS pipe N3 is connected with a with-writing bit line of the N1-P1 phase inverter. The NMOS pipe N4 is connected with a non-with-reading word line of a with-writing bit line of the N2-P2 phase inverter.

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