The invention discloses a method for optimizing the area of a mixed signal chip, which relates to the technical field of integrated circuit. The method of the invention comprises the following steps: (1) when designing an IP layout, separating resistors or capacitors out of the IP to reduce the IP area substantially; (2) arranging the prepared IP and other logic units to obtain the area of the whole chip; and (3) placing the resistors or the capacitors which are separated out on a chip power ring, under a pad or in a wiring area which is different from the metal layer used by the resistors orthe capacitors. Compared with the prior art, the invention ensures the IP performance and simultaneously reduces the IP area, further optimizes the chip area, does not generate a waste area, and saves the numbers of the resistors and the capacitors.