The invention discloses an integer division operational circuit tolerating errors. A signal processing device comprises an addressing device, a first left-position shifter, a second left-position shifter, a subtracter, a multiplying unit and a right-position shifter, wherein the addressing device is used for searching the highest nonzero digit of a divisor and outputting the highest digit byte value; the first left-position shifter carries out shifting processing according to the highest byte value and generates a first power coefficient; the second left-position shifter carries out shifting processing according to the highest byte value and generates a second power coefficient; the subtracter calculates out a multiplicator according to the divisor, the first powder coefficient and the second power coefficient and outputs the multiplicator to the multiplying unit; the multiplying unit carries out the multiplying according to the input value and the multiplicator and outputs the multiplied result to the right-position shifter; and the right-position shifter outputs the calculation result.