Provided is a power supply voltage monitoring circuit (50) including: a signal output circuit (1) for outputting a signal voltage (Vsignal) which exhibits a saturation characteristic with respect to an increase in a power supply voltage (VDD); and a signal voltage monitoring circuit (4) for comparing the power supply voltage (VDD) with the signal voltage (Vsignal), and outputting a signal (Vout) indicating that the signal voltage (Vsignal) is normal when there is a predetermined voltage difference. With this configuration, a minimum operating power supply voltage may be reduced in an electronic circuit, and the power supply voltage may be used with efficiency.