The invention provides a discrete cosine transform (DCT)-inverse discrete cosine transform (IDCT) coprocessor suitable for a system on chip (SOC). The DCT-IDCT coprocessor consists of a CP-BRIDGE module, a random access memory (RAM) module, a control and state register, a DCT-IDCT two-dimensional computation module, a DCT-IDCT one-dimensional computation module, an input buffer, an output buffer, a clip computation module and an add computation module. The DCT-IDCT coprocessor is directly connected with a coprocessor interface of a central processing unit (CPU) without being additionally articulated with an advanced high-performance bus (AHB) or an advanced periphery bus (APB) so as to save the bus resource of a system to a certain degree; and an RAM, which is used for storing data to be processed and processing results, can multiplex with other coprocessor. The DCT-IDCT coprocessor has the advantages of small area, high speed, lower power consumption and the like by rationally multiplexing a multiplier and regulating cycles of operation.