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发明公开
CN101794619A 页面缓冲电路和非易失性存储装置 无效 - 撤回

页面缓冲电路和非易失性存储装置
摘要：
本发明公开了一种页面缓冲电路和非易失性存储装置，该页面缓冲电路包括：感测放大单元，其配置成将参考电压与选择的存储块的位线的位线电压相比较，并且将感测节点的电压电平增加所述参考电压与所述位线电压之间的差，其中所述位线电压根据选择的存储单元的编程状态而经历改变；以及若干锁存电路，其配置成根据所述感测节点的电压电平来锁存编程验证数据。
摘要（英）：

The present invention discloses a page buffer circuit and a nonvolatile memory device. The page buffer circuit comprises a sense amplification unit configured to compare a reference voltage and a bit line voltage of a bit line of a selected memory block and to increase a voltage level of a sense node by a difference between the reference voltage and the bit line voltage, wherein the bit line voltage is subject to being changed according to a program state of a selected memory, and a number of latch circuits configured to latch program verification data according to the voltage level of the sense node.

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