A method for integrating Non-Volatile Memory (NVM) circuitry (18) with logic circuitry (20) is provided. The method includes depositing a first layer of gate material (16) over the NVM area and the logic area of a substrate (12). The method further includes depositing multiple adjoining sacrificial layers (22, 24, 26) comprising nitride, oxide and nitride (ARC layer) overlying each other. The multiple adjoining sacrificial layers (22, 24, 26) are used to pattern a select gate (16) and a control gate (32) of a memory transistor in the NVM area, and an ARC layer (22) of the multiple adjoining sacrificial layers (22, 24, 26) is used to pattern a gate (16) of a logic transistor in the logic area (20).