The invention relates to a quick locking control circuit of a pulse width control loop, comprising a phase inverter Q1 with an enabling end, a phase inverter Q2, a D-type trigger Q3 with an asynchronous zero-clearing end, a PMOS (P-channel Metal Oxide semiconductor) transistor PM1, an NMOS (N-channel Metal Oxide semiconductor) transistor NM1 and resistors R1 and R2. The circuit has simple structure and can ensure that the locking time of a pulse width control system is greatly reduced and the amplitude thereof is reduced by more than seven times. The circuit can ensure that the pulse width control loop system automatically resets when stopping by accident and the pulse width control loop system enters into a power saving mode after working normally and has very little power consumption and high reliability. The circuit is suitable for the pulse width control loop system with a charge pump.