The invention discloses an ESD protective circuit with a control circuit for an integrated circuit, which belongs to the technical field of electronics. A plurality of ESD protective circuits of the invention are controlled by a single control circuit so as to save the area of a silicon chip occupied by the control circuit. Simultaneously, a plurality of auxiliary ESD relief passages are arranged besides a master ESD relief passage. The control circuit is utilized to reduce the triggering voltage of the ESD protective circuit, prevent an internal circuit device connected in parallel with an ESD protective device from being broken down and switched on first to further cause the anti-ESD capacity reduction of the chip and make more uniform the starting of an MOS device with a multi-finger structure.