Disclosed is a display panel driving circuit comprising a shift register, with which unit circuits for generating signal line selecting signals (G1 to Gm) are stepwise connected, for outputting pulses formed of the signal line selecting signals (G1 to Gm), sequentially from an initial stage to a final stage. To each of the unit circuits, there are inputted clock signals (CK1 and CK2), either a gate start pulse signal (GSP) generated on the basis of a synchronizing signal (VSYNC) from the outside of the display panel driving circuit or the signal line selecting signals (G1 to Gm) generated at another stage, and a clear signal (CLR). The clear signal (CLR) is activated, in the case where the synchronizing signal (VSYNC) is abnormal, and no pulse is subsequently outputted from the shift register till the start of the next vertical scanning period. The constitution thus made can realize the display panel driving circuit which can suppress the display disturbance or the increase of the load on a power source in the case where the synchronizing signal (VSYNC) becomes abnormal.