A processor circuit having reduced power consumption includes an analog front end operative to receive an analog signal supplied to the processor circuit and to generate a digital signal indicative of the analog signal. The processor further includes a digital back end operative to generate a digital output signal as a function of the digital signal generated by the analog front end. A buffer is coupled between the analog front end and the digital back end. In a first mode of operation, the digital back end operates at a substantially same data rate as the analog front end and the buffer is bypassed. In a second mode of operation, the digital back end operates at a higher data rate than the analog front end and the buffer is used to store outputs of the analog front end.