The invention discloses the realization of a tile cache strategy in a graphics processing unit (GPU) based on tile based rendering, which comprises a tile writing part and a tile reading part. When a tile is written, a tile number is taken as an index according to primitive tiling results, the tile is written into a cache space corresponding to the tile, a local counter is simultaneously maintained and 1 is added to the counter of the written tile, wherein a specific address of the cache space is obtained by calculation. When the tile is read, image information stored in the tile is sequentially read out according to values of the counters of each tile and transmitted to a plotting module.