A signal reception device (2) includes a memory circuit (22). Data contained in a digital input signal transmitted from a signal transmission device (1) is written by using a clock separated/generated from the received digital input signal by using a PLL circuit (21) and read by using a reference clock of crystal accuracy from a reference clock generation circuit (24). Here, a difference between the clock and the reference clock is detected so as to correct the difference to reproduce the digital input signal. If the signal reception device (2) delays as compared to the signal transmission device (1), the data contained in the digital input signal is thinned. If the signal reception device (2) advances as compared to the signal transmission device (1), a signal generated from the preceding and the following digital input signals is interpolated.