The device (14) has an input (141) connected with an input connection (21), an output (142) connected with an output connection (22), and a clock terminal (143) connected with a clock connection (23). The input connection, output connection and the clock connection are formed as differential communication links with two spacers, where the device is formed such that data bits are transferred at 100 mega baud during change of rising and falling clock edges. An access unit (13) is provided for directly accessing a memory (12) of a computing unit (11).