A circuit comprises a first read bit line, a second read bit line, and a sense amplifier. First and second read bit lines couple a plurality of memory cells and a reference cell of a memory array, respectively. The sense amplifier is configured to receive the first read bit line as a first input and the second read bit line as a second input. When a memory cell of the first plurality of memory cells is read, the memory cell is read activated, the first reference cell is configured to be off, the second reference cell is configured to be on, and the sense amplifier is configured to provide an output reflecting a data logic stored in the memory cell based on a voltage difference between a first voltage of the first read bit line and a second voltage of the second read bit line.