The invention belongs to the technical field of electronics, specifically, discloses an FPGA (Field Programmable Gate Array) timing driven layout method with timing constraints. According to the layout method provided by the invention, four types of timing constraints are proposed as follows: a clock period constraint, an input output delay constraint, a specific timing path constraint and a wire network maximum delay constraint. The main idea for processing the four types of timing constraints is to add the information of the timing constraints into a timing analysis step to process the timing constraints as a part of a final cost function. The method provided by the invention can process the timing constraints set by the users, so that the flexibility of an FPGA timing layout algorithm is increased greatly, and simultaneously, the correctness of the layout algorithm also can be guaranteed.