The invention relates to a semiconductor technique, in particular to a horizontal integrated standard super-junction SOI semiconductor power device comprising n+ buried layers. A cellular structure of the horizontal integrated SOI semiconductor power device comprises a substrate, an oxygen buried layer and an SOI layer which are sequentially overlapped and further comprises a high-voltage p LDMOS, a high-voltage n LDMOS and a low-voltage CMOS. The high-voltage p LDMOS, the low-voltage n LDMOS and the low-voltage CMOS are arranged on the SOI layer, and the high-voltage n LDMOS is arranged between the high-voltage p LDMOS and the low-voltage CMOS. The horizontal integrated standard super-junction SOI semiconductor power device is characterized in that the high-voltage p LDMOS, the low-voltage n LDMOS and the low-voltage CMOS are mutually separated through a shallow groove dielectric separating area and interlevel dielectrics, the interlevel dielectrics are connected with the upper surface of the oxygen buried layer, and the shallow groove dielectric separating area is arranged on the upper surfaces of the interlevel dielectrics. The horizontal integrated standard super-junction SOI semiconductor power device has the advantages of achieving various 100V-700V high-voltage devices with excellent performance and being high in speed, high in integration and low in conduction loss. The horizontal integrated standard super-junction SOI semiconductor power device is especially suitable for the field of horizontal integrated standard super-junction SOI semiconductor power devices.