A method of manufacturing a thin film transistor array panel includes forming a semiconductor on a substrate, forming a gate insulating layer on the semiconductor, forming a sacrificial layer including an opening on the gate insulating layer, forming a copper layer on the sacrificial layer, the copper layer filling the opening, forming a gate wiring by polishing the copper layer by chemical mechanical polishing until the sacrificial layer is exposed, removing the sacrificial layer, forming a source region and a drain region by doping conductive impurities on the semiconductor by using the gate wiring as a mask, forming a first interlayer insulating layer covering the gate wiring, and forming a source electrode and a drain electrode connected to the source region and the drain region, respectively, on the first interlayer insulating layer.