A liquid crystal display device includes a substrate (110); first signal lines (SL1) disposed on the substrate (110) and extending in the y-direction; a gate insulating layer (140) disposed on the first signal lines (SL1); a first electrode (173, 175) disposed on the gate insulating layer (140); a thin film transistor (Q) connected to one of the first signal lines (SL1) and including the gate insulating layer (140) and the first electrode (173, 175); a pixel electrode (191) extending in the y-direction connected to the thin film transistor (Q) and configured to receive a data voltage from the thin film transistor (Q); a common electrode (131, 133, 135) overlapping with at least a portion of the pixel electrode (191); and a first insulating layer (180b) disposed between the pixel electrode (191) and common electrode (131, 133, 135). The pixel electrode (191) or the common electrode (131, 133, 135) has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the first signal lines (SL1). At least a portion of the common electrode (131, 133, 135) overlaps with at least a portion of the first signal line (SL1). Since the gate insulating layer (140) is disposed on the first signal line (SL1), the parasitic capacitance between the first signal line (SL1) and the common electrode can be reduced.