The invention belongs to the technical field of SerDes serial communication and particularly relates to a malposition detection and error correction circuit in the SerDes technology. The malposition detection and error correction circuit in the SerDes technology is composed of a sending end digital circuit and a receiving end digital circuit. At the sending end, a check code generation circuit is started by a sending end controller to sequentially generate an N-digit full-1 synchronizing signal and a check signal with only the most significant digit being 0, and the N-digit full-1 synchronizing signal and the check signal are gated and sent to a Serializer module through an either-or MUX and then are transmitted to the receiving end digital circuit after passing through a difference transmission channel and a Deserializer; at the receiving end, a malposition detection circuit detects and judges whether malposition occurs on received data; the correct data bit order is obtained through recovery and correction by means of an error correction circuit module according to the bit number, actually appearing, of 0 in a received check node, and finally the correct data bit order is output. The malposition detection and error correction circuit in the SerDes technology is obtained through a digital circuit and has the advantages that programmability is achieved, the logic is simple, and the flexibility is good. The malposition detection and error correction circuit in the SerDes technology is compatible with the design flow of a digital integrated circuit design which is commonly used at present and based on the hardware description language.