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CN104050112B 用于标记需要写回持久存储的非事务代码区的开头和结束的指令 有权

用于标记需要写回持久存储的非事务代码区的开头和结束的指令
摘要：
提供了用于标记需要写回持久存储的非事务代码区的开头和结束的指令。所描述的处理器具有到非易失性随机存取存储器的接口和逻辑电路。该逻辑电路用于标识事务所修改的高速缓存行，该事务将易失性随机存取存储器看作该事务的持久存储。该逻辑电路还用于标识与事务不同的软件进程所修改的高速缓存行，该软件进程也将所述非易失性随机存取存储器看作持久存储。
摘要（英）：

A processor in described having an interface to non-volatile random access memory and logic circuitry. The logic circuitry is to identify cache lines modified by a transaction which views the non-volatile random access memory as the transaction's persistence storage. The logic circuitry is also to identify cache lines modified by a software process other than a transaction that also views said non-volatile random access memory as persistence storage.

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