The invention provides an IP core based on the JESD204 protocol and aims to provide an IP core which is strong in anti-interference capability high in transmission rate and unaffected by inter symbol interference and synchronous influence. The IP core based on JESD204 protocol is realized by adopting the following technical proposal; FPGA ( Field Programmable Gate Array) contains multiple GTX interfaces; each GTX interface receives data conforming to the JESD 204 protocol through a pair of differential signaling wires between an analog-digital converter ADC chip and each GTX interface in a serial manner; the IP core based on the JESD 204 protocol is characterized in that a clock generation unit generates all the input clocks required by all the other functional units; a reset function unit logically controls and generates reset signals, so as to receive control signals generated by a control state machine; a physical layer calls a high-speed serial transceiver inside the FPGA, so as to send converted parallel data to a data error detection function unit; the parallel data is further sent to a K code detection function unit for K code detection; the detected k code is sent to a K code count function unit for counting; a link synchronization function unit judges the synchronous state of a high-speed serial transmission link according to the detection results of the K code detection function unit; a data delay function unit conducts a delay treatment on the data from the GTX and provides the delay processed data for a K code substitution function unit.