The invention relates to a system and method for reducing power consumption in a semiconductor device. The method of making a first timing path (406, 408) includes developing a first design of the first timing path with a first logic circuit (406) and a first functional cell (408), wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design (214) is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor.