The invention discloses a verifying device for phase accuracy of an analog input merging unit. The verifying device is mainly composed of a CPU (central processing unit), an FPGA (field programmable gate array), an Ethernet MAC, an Ethernet PHY, an Ethernet optical fiber receiver, a universal optical fiber receiver, a D/A (digital to analog) converter, a temperature-compensation crystal oscillator, a low-pass filter, an A/D (analog to digital) converter, a precise transformer and a local bus. The CPU, the FPGA, the A/D converter and the D/A converter are connected with one another through the local bus, and the CPU accesses data of the FPGA, the A/D converter and the D/A converter through the local bus. An external clock unit outputs a light IRIG-B code time signal to the verifying device, a to-be-tested merging unit and an alternating-current analog signal source to enable the verifying device and the to-be-tested merging unit to synchronize, and meanwhile frequency accuracy of the alternating-current analog signal source is guaranteed, so that phase accuracy verification is realized.