利索-全球专利检索

  1. Login
  2. Sign Up
Invention Grant
CN104375972B 用于可配置数学硬件加速器的微处理器集成配置控制器 有权 转让

用于可配置数学硬件加速器的微处理器集成配置控制器
Abstract:
本发明涉及微处理器电路，包括软件可编程微处理器核心和数据存储器。数据存储器包括根据多个可配置数学硬件加速器的各自预定数据结构规格结构化的多组配置数据和用于多个可配置数学硬件加速器的各自输入数据组，每个可配置数学硬件加速器被配置将预定信号处理函数应用至输入数据组。配置控制器经由数据存储器总线耦合至数据存储器且耦合至多个可配置数学硬件加速器。配置控制器被配置从数据存储器的预定地址空间获取每个数学硬件加速器的配置数据组，将多组配置数据转译成多个可配置数学硬件加速器的各自的寄存器级配置数据组，将每组寄存器级配置数据传输至对应可配置数学硬件加速器以及写至对应可配置数学硬件加速器的一个或多个配置寄存器。
Abstract(English):

A microprocessor circuit may include a software programmable microprocessor core and a data memory accessible via a data memory bus. The data memory may include sets of configuration data structured according to respective predetermined data structure specifications for configurable math hardware accelerators, and sets of input data for configurable math hardware accelerators, each configured to apply a predetermined signal processing function to the set of input data according to received configuration data. A configuration controller is coupled to the data memory via the data memory bus and to the configurable math hardware accelerators. The configuration controller may fetch the configuration data for each math hardware accelerator from the data memory and translate the configuration data. The configuration controller may transmit each set of configuration data to the corresponding configurable math hardware accelerator and write the configuration data to configuration registers of the math hardware accelerator.

Public/Granted literature
Patent Agency Ranking
0/0