A mainboad comprises an interface, an identification module, a selection module, a SATA signal processing module, and a USB signal processing module. The identification module is connected with the interface to identify the device connected with the interface; if the interface is connected with a SATA device, the identification module outputs a first signal; if the interface is connected with a USB device, the identification module outputs a second signal; the signal terminal of the selection module is connected with the identification module; the selection module further comprises a first terminal, a second terminal and a third terminal; the first terminal is connected with the interface; when the signal terminal of the selection module receives the first signal, the selection module connects through the connection between the first terminal and the second terminal, whereas cuts off the connection between the first terminal and the third terminal; when the signal terminal of the selection module receives the second signal, the selection module connects through the connection between the first terminal and the third terminal, whereas cuts off the connection between the first terminal and the second terminal; the SATA signal processing module is connected with the second terminal of the selection module; and the USB signal processing module is connected with the third terminal of the selection module. The mainboard is high in compatibility.