The embodiment of the invention discloses a reset circuit applied to radio frequency identification. The reset circuit comprises a low-drop-out linear voltage stabilizer LDO used for outputting output voltage VDD, a band-gap reference source used for outputting reference voltage VREF, a comparator used for comparing the output voltage VDD and the reference voltage, a D trigger used for delaying a signal output by the comparator according to a delay clock signal, an paraphase amplifier used for receiving the signal output by the D trigger and conducting reversed phase amplification and an NAND gate used for conducting phase and on the signal processed by the paraphase amplifier and obtaining a reset signal. According to the reset circuit, numbers are reset through the reset signal, the problem that the power consumption is excessively large or reset fails in the number reset process is solved, many intermediate states can be avoided, and the reliability of the numbers is improved.