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发明授权
CN104795502B 一种半导体结构及其蚀刻方法 有权

一种半导体结构及其蚀刻方法
摘要：
本发明提供了一种半导体结构的蚀刻方法，所述半导体结构包括第一组绝缘层，位于所述第一组绝缘之上的第二组绝缘层，以及位于所述第二组绝缘层之上的第三组绝缘层，所述第一组绝缘层、所述第二组绝缘层、所述第三组绝缘层均包含一层或多层含硅绝缘层；所述蚀刻方法包括：以摩尔比为第一比例的CF4与C4F6的混合气为蚀刻气体蚀刻所述第三组绝缘层；以摩尔比为第二比例的CF4与C4F6的混合气为蚀刻气体蚀刻所述第二组绝缘层；及以C4F6为蚀刻气体蚀刻所述第一组绝缘层。本发明所提供的蚀刻方法，采用不同比例的蚀刻气体对各层进行蚀刻，使半导体结构的蚀刻孔的角度控制在50°‑80°之间，且对多晶硅具有很高的选择比。
摘要（英）：

The invention provides a semiconductor structure etching method. The semiconductor structure comprises a first insulated layer group, a second insulated layer group located above the first insulated layer group, and a third insulated group located above the second insulated layer group, wherein each of the first insulated layer group, the second insulated layer group and the third insulated layer group comprises one or multiple layers of silicon-containing insulated layers. The etching method comprises: a mixed gas of CF4 and C4F6 with a molar ratio to be a first ratio serves as an etching gas to etch the third insulated layer group; a mixed gas of CF4 and C4F6 with a molar ratio to be a second ratio serves as an etching gas to etch the second insulated layer group; and C4F6 serves as an etching gas to etch the first insulated layer group. According to the etching method provided by the invention, etching gases of different ratios are adopted to etch each layer, an angle of an etching hole of the semiconductor structure is controlled between 50 DEG to 80 DEG, and polycrystalline silicon has a high selection ratio.

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