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发明公开
CN104931826A 模拟量输入式合并单元的相位误差测试装置及方法 无效 - 驳回

模拟量输入式合并单元的相位误差测试装置及方法
摘要：
本发明公开了一种模拟量输入式合并单元的相位误差测试装置，包括：功率源、网卡、FPGA芯片、SAR ADC和CPU，所述功率源分别连接待测合并单元、所述SAR ADC和所述CPU，所述网卡分别连接所述待测合并单元和所述FPGA芯片，所述FPGA芯片还分别连接所述CPU和所述SAR ADC，所述SAR ADC也连接所述CPU。本发明还公开了一种模拟量输入式合并单元的相位误差测试方法。本发明能够在不改变现场接线结构的方式下完成测试，不需要停电测试，测试结构稳定可靠。
摘要（英）：

The invention discloses a phase error test device and method of an analog input type merging unit. The phase error test device includes a power source, a network card, an FPGA chip, an SAR ADC and a CPU, wherein the power source is connected with a merging unit to be tested, the SAR ADC and the CPU respectively, the network card is connected with the merging unit to be tested and the FPGA chip respectively, the FPGA chip is connected with the CPU and the SAR ADC respectively, and the SAR ADC is connected with the CPU. The invention also discloses a phase error test method of an analog input type merging unit. With the phase error test device and method of the analog input type merging unit of the invention adopted, tests can be accomplished with a field wiring structure unchanged, and can be performed without power outage required, and a test structure is stable and reliable.

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