The invention provides a system for testing the bit error rate (BER) of a high-speed serial chip. The system comprises a tested board, a control module, a BER testing module, a clock phase-locking module, and a host computer. The tested board is provided with a high-speed serial chip to be tested. The control module is connected with the tested board and is used for counting time and executing interruption control of a system BER test. The BER testing module is connected with the tested board and is used for testing the BER of the tested board. The clock phase-locking module is connected with the control module, the tested board, and the BER testing module, and is used for receiving a control command transmitted from the control module, generating required testing clocks with various frequencies, and supplying the testing clocks to the tested board and the BER testing module. The host computer is connected with the BER testing module and is used for setting a testing mode and displaying a tested result. The system is simple and easy to use, good in universality, and capable of increasing the BER testing efficiency of a high-speed serial chip data transmission system.