A dynamic and static mixed adder comprises a static part and a dynamic part, wherein the output end of the static part is connected with the input end of a first phase inverter; the first phase inverter is used for outputting a carry signal; the output end of the static part is further connected with the dynamic part; the dynamic part is used for finishing summation operation of addition; the output end of the dynamic part is connected with a second phase inverter; the dynamic part comprises a summing circuit and a potential holding circuit; the summing circuit is used for finishing summation operation of addition; and the potential holding circuit is connected with the output end of the second phase inverter and used for compensating charge of a floating node and reducing signal scramble during operation of the adder. The adder is simple in circuit form, slightly influenced by change of process parameters and capable of effectively working in a low-voltage environment; and through the potential holding circuit, originally the signal scramble in the operational process is avoided, the power consumption is reduced, and the energy utilization efficiency is highest near a critical voltage value.