The invention discloses a wafer-level chip TSV packaging structure and a packaging method thereof. The packaging structure comprises a plurality of chip units arranged in an array, the chip units are provided with a plurality of TSV structures, a plurality of cutting lines are formed between adjacent chip units, the chip units comprise first surfaces and second surfaces which are opposite to each other, the peripheries of the first surfaces are provided with a plurality of welding window openings connected with the TSV structures, the welding window openings in the same chip unit are provided with one and only one symmetric axis, and the welding window openings in adjacent chip units are symmetrically distributed along the cutting lines disposed between the adjacent chip units. According to the invention, the welding window openings in adjacent chip units are symmetrically distributed along the cutting lines, during cutting, surface stresses applied to adjacent chip units are the same, chip fragmentation caused by uneven stresses can be avoided, and the packaging efficiency and the chip yield are improved.