The invention discloses a method and a device for reducing chip system power consumption, and an intelligent transformer substation debugging instrument. The method for reducing chip system power consumption is used for reducing power consumption of a chip system, wherein the chip system comprises at least two chips which establish a communication link. The method comprises the steps of: monitoring data received by the chip system, and judging working conditions of chips in the chip system; and controlling system clocks of the chips according to the working conditions, and/or adjusting working conditions of related ports on the chips, wherein the system clocks are frequency-variable dynamic system clocks, and frequency of each dynamic system clock adapts to the working condition thereof. The invention further discloses the corresponding device and the intelligent transformer substation debugging instrument using the same. The method and the device are capable of effectively reducing power consumption of multi-chip systems.