An output circuit includes: an output portion which includes a plurality of output blocks each of which converts 2-bits parallel data to 1-bit serial data and outputs the converted serial data; a control signal generation circuit; a first clock generation portion; and a plurality of second clock generation portions which individually generate second clocks, wherein each of the output blocks includes: a latency expansion circuit which sequentially latches the 2-bits parallel data according to the reference clock and an inverted reference clock, selects two from the latched data signals based on the latency adjustment signal; and two-clocks flip-flop circuit which latches one of two outputs from the latency expansion circuit in synchronization with the second clock corresponding to the output block and latches the other of the two outputs from the latency expansion circuit in synchronization with the inverted second clock.