The invention provides a verifying method and apparatus for an FPGA (Field-Programmable Gate Array) boundary scan system, which are used for debugging the FPGA boundary scan system on a simulation platform. The method includes the following steps: verifying the simulation characteristics of an IO module of an FPGA through an input instruction/output instruction, wherein the verifying step includes verifying the input characteristics of the IO module and verifying the output characteristics of the IO module; verifying instruction processing of the boundary scan system, wherein instructions include a sampling input instruction, an output test instruction, an output enhancement test instruction and an output training test instruction; and verifying internal connection of the boundary scan system and the FPGA through an internal test instruction, wherein a round trip pathway of the FPGA is gated through user configuration. The verifying method and apparatus can comprehensively and thoroughly verify the FPGA boundary scan system and ensure correctness of functions of the FPGA boundary scan system.