Disclosed is a flash memory decoding circuit testing method. A flash memory decoding circuit comprises storage units in m-row n-column array arrangement, wherein m and n are positive even numbers. In a same column, starting from a first storage unit, each two adjacent storage units are of an image symmetric structure and are connected with a same word line. The flash memory decoding circuit testing method includes: dividing the storage units in m rows and n columns into a 2s-row s-column array; testing corresponding row decoders and column decoders according to a following sequence: testing the row decoder and the column decoder corresponding to the storage unit in the kth column and the 2k-1st row, and testing the row decoder and the column decoder corresponding to the storage unit in the kth column and the 2kth row, wherein s is a positive integer, 2s is less than or equal to m and less than or equal to n, and k is an integer from 1 to s. By using the testing method, storage unit arrays with image symmetric structures can be tested comprehensively and effectively.