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发明授权
CN105930241B EMMC接口和NAND接口的相位调整方法及装置 有权

EMMC接口和NAND接口的相位调整方法及装置
摘要：
本发明提供一种EMMC接口和NAND接口的相位调整方法及装置，在首次正常工作模式前对PCB板的自适应训练，测试激励数据按照预先存储的数据序列的传输时钟频率送出，经两级寄存器延迟后送出主控芯片的数据引脚端口，然后经过PCB导线传输至EMMC或NAND器件的数据pin脚；同时EMMC或NAND的数据传输时钟依次经过相位延迟和寄存器延迟后输出至主控芯片的时钟引脚端口,然后经过PCB导线传输至EMMC或NAND器件的时钟pin脚；通过控制所述相位延迟和寄存器延迟，直至找到最佳匹配PCB板级相位延迟的芯片内部相位延迟配置，以供主控芯片在正常工作时进行EMMC或NAND数据传输。这样就可以和不同PCB电气条件达到最佳的匹配效果。
摘要（英）：

The present invention provides a method and an apparatus for adjusting phases of an EMMC interface and a NAND interface. The method comprises that before a first normal operation mode, adaptive training is carried out on a PCB board, and test stimulus data is sent out according pre-stored transmission clock frequency of a data sequence, and after undergoing a two-stage register delay, the data is sent to a data pin port of a master chip, and is transmitted through a PCB wire to a data pin of the EMMC or the NAND device; simultaneously, after sequentially undergoing a phase delay and the two-stage register delay, a data transmission clock of the EMMC or the NAND is output to a clock pin port of the master chip, and is transmitted through the PCB wire to a clock pin of the EMMC or the NAND device; and the phase delay and the two-stage register delay are controlled until a chip exterior phase delay chip configuration optimally matched with the PCB board level phase delay, so as to enable the master chip to carry out EMMC or NAND data transmission during normal operation. Thus, optimal match effects under different PCB electrical conditions can be reached.

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