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发明公开
CN106066843A 一种高速Base64并行编解码装置 无效 - 驳回

一种高速Base64并行编解码装置
摘要：
本发明公开了一种高速Base64并行编解码装置，其特征在于，包括用于数据理的编码模块和解码模块，其中编码模块包括：至少一个数据接收模块，至少一个编码控制模块，至少一个数据发送模块，解码模块包括：至少一个数据接收模块，至少一个解码控制模块，至少一个数据发送模块；本发明基于FPGA平台，实现了Base64编解码的16字节的并行处理，提升了Base64编解码的效率，并有效降低了CPU的资源消耗。
摘要（英）：

The invention discloses a high speed Base 64 parallel coding and decoding device characterized by comprising a coding module and a decoding module used for data processing; the coding module comprises at least one data reception module, at least one coding control module, and at least one data emission module; the decoding module comprises at least one data reception module, at least one decoding control module, and at least one data emission module; the high speed Base 64 parallel coding and decoding device can realize Base 64 coding and decoding 16-byte parallel processing through a FPGA platform, thus improving Base 64 coding and decoding efficiency, and effectively reducing CPU resource consumption.

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