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发明公开
CN106297686A 像素内存储单元、像素内数据存储方法以及像素阵列 有权

像素内存储单元、像素内数据存储方法以及像素阵列
摘要：
公开了一种像素内存储单元及数据存储方法、以及像素阵列。所述像素内存储单元包括：数据输入电路，其被配置为在第一控制信号端的第一控制信号处于其有效电平时将数据线上的数据电压读取到第一数据锁存端和第二数据锁存端上；第一数据锁存电路，其被配置为保持所述第一数据锁存端的电平；第二数据锁存电路，其被配置为保持所述第二数据锁存端的电平；驱动控制电路，其被配置为使驱动节点的电平与所述第一数据锁存端的电平相反；以及驱动电路，其被配置为在所述驱动节点处于其有效电平时将第三电源电压端的第三电源电压输出至输出端并且在所述第二数据锁存端处于其有效电平时将第四电源电压端的第四电源电压输出至所述输出端。
摘要（英）：

The invention discloses a pixel internal memory unit, a data storage method, and a pixel array. The pixel internal memory unit includes a data input circuit, a first data latch circuit, a second data latch circuit, a driving control circuit and a driving circuit. The data input circuit enables a digital voltage of a data line to be applied over a first data latch end and a second data latch end when a first control signal of a first control signal end is at an active level. The first data latch circuit is configured to maintain the level of the first data latch end. The second data latch circuit is configured to maintain the level of the second data latch end. The driving control circuit is configured to enable the level of a driving node to be opposite to the level of the first data latch end. The driving circuit is configured to output a third power voltage of a third power voltage end to an output end when the driving node is at an active level thereof, and outputs a fourth power voltage of a fourth power voltage end to the output end when the second data latch end is at an active level thereof.

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