The invention provides an automatic verifying platform of a programmable logic block based on System Verilog, comprising a top layer testing module, a testing excitation automatic generating module, a virtual interface connecting module, an algorithms library, a reference module establishing module and an automatic checking module. The top layer testing module starts a testing command, and data is generated by an automatic motivation generating module, and transmitted to a tested object and the reference model through the virtual interface connecting module; after receiving the data, the tested object treats the data as required; the reference model also treats the data; at last, the tested object and the reference model transmit the generated to the automatic checking module through the virtual interface connecting module so as to carry out the comparison treatment; the checking module outputs the comparison result. By applying the virtual interface method of System Verilog, the testing platform is separated from the tested object, thus the testing platform is not greatly changed along with the change of the testing object, and the reusing rate is high.