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发明公开
CN106933319A 一种变流器DSP上电复位控制方法 无效 - 撤回

一种变流器DSP上电复位控制方法
摘要：
一种变流器DSP上电复位控制方法，双处理器监控芯片U1与CPLD芯片U2连接，CPLD芯片U2与DSP芯片U3连接，在变流器上电之后，当1.9V电源电压未达到1.68V时，双处理器监控芯片U1产生低电平，CPLD芯片U2采集通过逻辑算法将双处理器监控芯片U1的状态赋值给DSP芯片U3使得DSP芯U3片处于复位状态；当1.9V电源电压达到1.68V时，双处理器监控芯片U1延迟200ms，翻转为高电平，CPLD芯片U2根据采集的上升沿和DSP芯片U3提供的低速时钟信号CLK来进行脉冲计数算法来产生1个高电平为21us，低电平为34us的复位脉冲，复位脉冲通过CPLD芯片U2输出给DSP芯片U3来给DSP芯片U3复位1次，复位完成之后CPLD芯片U2将双处理监控芯片U1的电平状态赋值给DSP芯片U3。
摘要（英）：

The invention discloses a DSP power-on reset control method for a converter. A dual-processor monitoring chip U1 is connected with a CPLD chip U2, and the CPLD chip U2 is connected with a DSP chip U3. After the converter is powered on, when 1.9V supply voltage does not reach 1.68V, the dual-processor monitoring chip U1 generates a low level, and the CPLD chip U2 performs collection to assign the state of the dual-processor monitoring chip U1 to a DSP chip U3, so that the DSP chip U3 is in a reset state; when the 1.9V supply voltage reaches 1.68V, the dual-processor monitoring chip U1 delays 200ms and turns into a high level, the CPLD chip U2 performs a pulse counting algorithm according to a collected rise edge and a low-speed clock signal supplied by the DSP chip U3 to generate a reset pulse with a high level of 21us and a low level of 34us, the reset pulse is output to the DSP chip U3 through the CPLD chip U2 to reset the DSP chip U3 once, and after reset is completed, the CPLD chip U2 assigns the level state of the dual-processor monitoring chip U1 to the DSP chip U3.

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